Gate driver on array (GOA) techniques have been widely used in LCD design. This structure not only saves the expenses of the gate driver chips, but also reduces the width of side frame of the LCD to allow a narrow side frame structure.
As the size and the resolution of the LCD increase, the clock signals (CK) for the GOA circuits become various. In general, a high definition (HD) panel (e.g., the resolution is 1280*720) uses 4 clock signals in the GOA circuits. Furthermore, a full high definition (FHD) panel utilizes 6 or 8 clock signals. The clock signal is a high-frequency signal in which a high voltage level and a low voltage level switch frequently. However, the power consumption of the gate driver is related to the power consumptions of transistors caused by crossing currents passing through the transistors. In addition, the power consumption of the transistors is proportional to the squared switching frequency of the clock signal. Therefore, if the number of the clock signal is larger or the frequency of the clock signal is higher, the power consumption of the gate driver is significant.
Please refer to FIG. 1. The GOA circuit 100 comprises 4 transistors and 1 capacitor. The GOA circuit of current stage outputs a gate driving signal G(n) and provides an intermediate signal, which is a starting signal ST(n), to a GOA circuit of next stage. The GOA circuit 100 comprises a main driving circuit 120 and an output circuit 150. The main driving circuit 120 comprises a transistor T1 and a transistor T2. The transistor T1 is turned on in response to a starting signal ST (n−2). The transistor T2 is turned on to transmit the voltage source Vss to reset the signal Q(n) in response to a gate driving signal G(n+2) being received.
The output circuit 150 comprises a transistor T2, a transistor T4, and a transistor T8. The transistor T4 is turned on in response to signal Q(n). When the transistor T4 is turned on, the clock signal CK is transferred to the source and thus the gate driving signal G(n) is outputted. In addition, the transistor T8 is turned on in response to a gate driving signal G(n+2) and thus the voltage source Vss is transferred through the transistor T8 to reset the gate driving signal G(n).
Because of the reliability of amorphous silicon, a pull-down circuit 15 needs to be additionally provided. The pull-down circuit 15 is used to ensure the voltage levels of the node Q and the output node of the GOA circuit when the GOA circuit is in a deactivation state. In other words, the pull-down circuit 15 is able to pull down the voltage levels of the node Q and the output node and thus raise the reliability of the GOA circuit 100.
GOA circuit of a large-size high-definition display often adopts multiple clock signals, such as 6 or 8 clock signals, to ensure the reliability. Please refer to FIG. 2, which is a diagram of a conventional two-stage GOA circuit driven by 6 different phases. In FIG. 2, the first stage 210 of the GOA circuit generates three gate driving signals G(N), G(N+1), and G(N+2) in response to two gate driving signals G(N−1) and G(N+5) and six input clock signals CK1, CK2, CK3, XCK1, XCK2, and XCK3.
Please refer to FIG. 3, which is a timing diagram corresponding to operations of the GOA circuit. As shown in FIG. 3, the accumulated width of the gate driving signals G(N)−G(N+5) and the clock signals CK1-CK3 and XCK1-XCK3 is 3W. W is a time period of charging a single scan line. The power is mainly consumed due to the clock signals. In general, the power consumption is proportional to the voltage of the clock signals squared. Therefore, if the number of the clock signals is larger, the power consumption is more significant. This problem becomes more severe when the resolution of the display is higher. Furthermore, the large number of the clock signals also increases the cost of the driving circuit and thus reduces its competitiveness.
Therefore, a new structure of GOA is required to solve the above-mentioned problem of a large number of clock signals and huge power consumption. This new structure may reduce the number of clock signals and reduce the power consumption of the GOA circuit to meet the demands of green products.